As communication networks scale up in terms of speed and capacity, packets being switched and routed through network nodes need to be processed at increasingly higher speeds, matching those of the communication network links. Additionally, the processing per packet is becoming more complex. For example, the processing involves not only determining the destination of the packet but the processing of security parameters of the packet. A switching device architecture such as that of an Ethernet switch must accommodate the ever increasing performance needed for next generation high-speed networking.
The switching device redirects each incoming packet on an ingress port to an egress port based on information in the packet header. The switch must accommodate packets of various byte-lengths while still meeting higher and higher speed requirements.
Data integrity is a concern as well. For example, prevention of a queue filling up and overflowing which would result in bits being dropped must be addressed in a switch architecture. In some architectures, the minimum buffer size used is the number of bits in a maximum sized packet to address this problem. This results in larger buffer sizes in which memory is not fully utilized.
One may also consider the case where a packet is split into several cells to reduce latency in the switch caused by large packets. The switch architecture must provide for reliable reassembly of the cells into its original packet. Switch architectures desire to process packets from ingress to egress in a manner that is fast and reduces the burden on buffering and the amount of information needed for reassembly.